Different ways to Fix Setup or Hold VIOLATIONS in a design during PnR

How do I fix setup or hold violation during placement?

Setup and hold violations represent crucial timing constraints that can arise during the placement phase of digital circuit design, especially within ASIC and FPGA implementations. The following outlines a comprehensive methodology for identifying and rectifying these violations.

Understanding Setup and Hold Violations

Setup Violation: A setup time violation occurs when the data input to a flip-flop is not stable prior to the arrival of the clock edge, potentially resulting in the incorrect latching of data.

Hold Violation: Data input instability, occurring immediately following the clock edge, may result in data corruption due to the flip-flop's inability to properly latch the input.

Steps to Fix Setup Violations

Analyze Timing Reports: Use timing analysis tools to identify the specific paths causing setup violations. Look for critical paths and their delays.

Optimize Logic:

- Restructure Logic: Simplify or reorganize the logic to reduce the combinational path delays.

- Use Faster Logic Elements: If possible, replace slower gates with faster alternatives.

Increase Clock Period: If feasible, consider increasing the clock period to allow more time for signals to propagate.

Reposition Components: During placement, try to reduce the distance between flip-flops and their driving logic to minimize routing delay.

Add Buffers: Inserting buffers in critical paths can help drive the load and reduce delay.

Adjust Constraints: Review and adjust constraints in your design tools, such as clock definitions and false paths, to ensure accurate timing analysis.

Use Multi-Cycle Paths: If certain paths do not need to meet the setup time in every clock cycle, you can define them as multi-cycle paths.

Steps to Fix Hold Violations

Analyze Timing Reports: Similar to setup violations, use timing analysis tools to identify paths with hold violations.

Add Delay: Insert delay elements (like buffers) to increase the signal delay on paths that are too fast.

Reposition Components: Move the flip-flops or their driving logic closer to each other to minimize the routing delay.

Reduce Load: If possible, redesign the logic to decrease the capacitance seen by the flip-flops.

Use Faster Cells: Replace slower cells with faster ones that can provide the required timing margins.

Clock Skew: If applicable, consider adjusting clock skew to provide additional hold time for critical paths.

What is blockage and halos in physical design in VLSI?

Blockages:

Let’s assume that for some reason you don’t want to place any logic (can be a specific set of cells as well) or you don't intend to allow certain metal layers in a specific area or you are reserving a space for later stage additions (could be a room for top design related ) :

in all these cases you can use ‘blockages’ to reserve/restrict/block a specific area either from preventing std cell placement or avoiding specific layer metal shapes.

  1. placement blockages

  2. routing blockages.

Halos:

In the design of a System-on-Chip (SoC) comprising multiple sub-IPs/blocks, the physical implementation of both the top-level SoC and its sub-blocks is typically managed by distinct teams. To ensure that the physical layout adheres to design rules and is fabrication-ready upon integration, a coordinated approach is essential. This involves guidance from the methodology, fabrication, and process teams to establish standardized layout patterns for all designs, particularly at their boundaries. This best practice enables the top-level designer to anticipate interface patterns and implement integration strategies effectively. To facilitate this, the implementation of HALO cells, incorporating recommended patterns for various edge types, is proposed. Both sub-blocks and the top-level design must utilize these HALO cells appropriately on all sides. 

Why do we start with clock routing first in physical design?

Typically, most designs incorporate clocks, with a substantial number of sequential cells governed by these clock signals. The prioritization of routing is not solely determined by whether clocks or data are considered first; rather, it hinges on factors such as criticality, vulnerability to variations, operational frequency, load magnitude, and the distance required for signal propagation to all sinks. In synchronous designs, clocks serve as the primary control signals for sequential cells. Given the clock network's high load, operational frequency, and stringent requirements for minimal variation, clock routing is initiated before data signal routing. This approach allows for greater flexibility in utilizing various Non-Design Rule (NDR) options and specific metal layers to meet specific timing objectives. Furthermore, in certain instances, the routing of exceptionally critical signals may commence even before clock routing.

Double Patterning

Double patterning is a lithographic technique employed in advanced integrated circuit manufacturing processes. It allows for the creation of sub-nanometer features on chips using existing optical lithography systems.

The implementation of double patterning presents certain challenges, including elevated mask and lithography expenses, and constraints on circuit layout, which can affect design complexity, device performance, variability, and density.

Double patterning mitigates diffraction effects in optical lithography, which arise because the minimum dimensions of advanced process nodes are significantly smaller than the 193nm wavelength of the light source. These diffraction effects compromise the accuracy of deep sub-micron patterns, causing blurring and potentially preventing the replication of small features from the mask onto the wafer.

To mitigate diffraction effects, such as shorts and opens, the original mask is partitioned into two distinct masks, designated as Mask A and Mask B. This approach, however, escalates mask costs (lithography expenses) due to the implementation of double patterning and introduces additional Design Rule Checking (DRC) constraints.

To address the increasingly significant diffraction challenges associated with each new process node, several reticle enhancement techniques have been developed.

Phase-shift masks, introduced at the 180nm process node, modify the phase of light passing through specific mask regions. This alteration influences diffraction patterns, thereby mitigating the defocusing effects associated with mask dimensions smaller than the illumination wavelength. A drawback of phase-shift techniques is the increased complexity and cost of mask fabrication.

Optical Proximity Correction (OPC) techniques involve pattern distortion on the mask to counteract diffraction effects. This is achieved, for example, by adding small "ears" to the corners of a square feature on the mask, ensuring sharp definition on the wafer. While effective, this technique introduces layout restrictions, computational overhead in design, and increases the time and cost associated with mask production..

TIE CELLS

To prevent direct gate connections to the power or ground network, tie-high and tie-low cells are employed. Within this design, certain cell inputs may necessitate a logic 0 or logic 1 value. Unused cell inputs are also connected to ground or power nets, as leaving them unconnected is not permissible. Rather than directly connecting these inputs to the VDD/VSS rails/rings, they are connected to specialized cells within the library, known as TIE cells

The tie-high, tie-low circuit, featuring tie-high and tie-low outputs, incorporates a regenerative device designed for connection to both outputs, along with at least one PMOS device and one NMOS device, intended for connection to a high voltage and a low voltage, respectively.

In integrated circuit (IC) applications, it is not always necessary to utilize all inputs. Unused inputs should be consistently maintained in a stable logic state, rather than left floating, as unpredictable or intermediate logic states can lead to unpredictable and inconsistent logical outcomes. This is a critical concern that IC designers actively address.

To ensure stability, small circuits are incorporated into ICs. These circuits typically provide at least two outputs: one consistently high and another consistently low. These outputs are then used to connect IC inputs to either a high or low state, thereby locking unused inputs into a stable logic state.

However, conventional circuit designs present several challenges. Many designs utilize at least four transistors, which consume valuable chip area and may necessitate additional, costly manufacturing steps. Furthermore, some designs, while using only three transistors, often exhibit limited tolerance to electrostatic discharge (ESD).

Consequently, there is a need in the field of integrated circuit design for improved, smaller circuits with enhanced ESD tolerance, capable of effectively tying unused IC inputs to either a high or low state.

Regarding the rationale for employing such circuits, gate oxide is inherently thin and sensitive to voltage surges. Certain manufacturing processes may restrict the direct connection of gates to power rails due to the potential for gate oxide damage from voltage surges, such as ESD events. Therefore, tie cells, which utilize diode-connected n-type or p-type devices, are often employed. This approach prevents direct gate connections to either power or ground.

This is the foundry's rationale for ESD protection against surges. Examining the schematic of the tie cells in a standard cell library may reveal an inverter configuration with its input connected to either VDD (for tie-low) or VSS (for tie-high). While this configuration still connects the tie cell's gate to the power rails, it offers benefits such as reduced leakage current. Additionally, it simplifies the process of rewiring during Engineering Change Orders (ECOs), particularly when swapping a 1'b1 for a 1'b0.

Skin Effect Impact on Semiconductor Wires

Currently, our analysis has assumed a linear and constant resistance for a semiconductor wire, which is generally accurate for most semiconductor circuits. However, at elevated frequencies, the skin effect introduces a frequency-dependent resistance.

High-frequency currents exhibit a tendency to concentrate on the conductor's surface, with current density decreasing exponentially with depth. The skin depth, denoted as d, is defined as the depth at which the current diminishes to e⁻¹ of its nominal value, and is expressed as:

Given the signal frequency (f) and the permeability of the surrounding dielectric (U), which typically approximates the permeability of free space (m = 4p ´ 10-7 H/m), the skin depth for Aluminum at 1 GHz is calculated to be 2.6 mm.

The impact of the skin effect can be approximated by assuming a uniform current distribution within an outer shell of the conductor, with a thickness denoted as d, as illustrated in the provided figure for a rectangular wire. Consequently, the effective cross-sectional area of the wire is approximated to 

we obtain the following expression for the resistance (per unit length) at high frequencies (f > fs):

The increased resistance at higher frequencies may cause an extra attenuation and hence distortion of the signal being transmitted over the wire. To determine the on-set of the skin-effect, we can find the frequency fs where the skin depth is equal to half the largest dimension (W or H) of the conductor. Below fs the whole wire is conducting current, and the resistance is equal to (constant) low-frequency resistance of the wire. From Eq. (4.6), we find the value of fs:

Physical design QNA

1. What is floorplanning?

    A. Floorplanning is the process of strategically positioning blocks and macros within the chip or core area, thereby defining routing regions. This process determines the die size and establishes wire tracks for standard cell placement. It also generates power straps and specifies Power Ground (PG) connections, as well as I/O pin/pad placement information. In essence, floorplanning involves determining macro placement, power grid generation, and I/O placement.

2. What constitutes a well-executed floorplan?

    A. A robust floorplan should adhere to the following constraints:

    * Minimize the overall chip area.

    * Facilitate the routing phase (ensuring routability).

    * Enhance performance by reducing signal delays.

3. What inputs are required for floorplanning?

    A. The following inputs are essential for floorplanning:

    * Synthesized Netlist (.v, .vhdl)

    * Design Constraints (SDC – Synopsys Design Constraints)

    * Physical Partitioning Information of the design

    * IO Placement file (optional)

    * Macro Placement File (optional)

    * Floorplanning Control parameters

4. What are the outputs of the floorplanning process?

    A. The floorplanning process yields the following outputs:

    * Die/Block Area

    * I/Os Placement

    * Macros Placement

    * Power Grid Design

    * Power Pre-routing

    * Standard cell placement areas

5. Given a netlist comprising 500k gates, how can the die area and floorplanning be estimated?

    A. There are two primary methods for estimating die area:

    Method 1:

    Each cell possesses an area value specific to the chosen library. By examining each cell and multiplying its count by its corresponding area from the vendor's library, a density factor can be applied. Typically, a standard design achieves approximately 80% density after placement. This data allows for an estimation of the required die area.

    Method 2:

    Alternatively, the design can be loaded into an implementation tool. By adjusting the floorplan (x and y coordinates), the initial utilization can be set to approximately 50% to 60%.

The approach is contingent upon the quality and completion status of the netlist, specifically the degree of completion, such as 75%, 80%, or 90%.

6. What is the methodology for floor planning in multi-Vdd designs?

A. The initial step involves defining the power domains, followed by the implementation of power rings for each domain and the addition of power stripes to supply power to standard cells.

7. What is the definition of core utilization percentage?

A. The core utilization percentage represents the proportion of the core area utilized for cell placement. This is calculated as the ratio of the total cell area (including hard macros, standard cells, and soft macro cells) to the core area. For instance, a core utilization of 0.8 indicates that 80% of the core area is used for cell placement, with 20% available for routing.

8. Does an increase in core utilization to 90% potentially lead to macros being placed outside the core area, and does this imply a reduction in width and height?

A. Operating at 90% utilization may introduce congestion and routing challenges, potentially hindering routing within the designated area. While it may be feasible to accommodate this utilization level initially, subsequent timing optimizations, such as upsizing and buffer insertion, can increase the size requirements. In such cases, adjustments to the floorplan may be necessary. Therefore, a safer approach is to maintain a utilization range of 70% to 80%.

9. Why is it necessary to remove all placed standard cells and then write out the floorplan in DEF format? What is the purpose of the DEF file?

A. The DEF file primarily focuses on the floorplan size. This method is employed to obtain an abstract representation of the floorplan. By saving and loading this file, the abstract can be restored, eliminating the need to redo the floorplan.

10. Can area recovery be achieved by downsizing cells along paths with positive slack?

A. Yes, area recovery can be accomplished by downsizing cells on paths exhibiting positive slack. Additionally, the removal of unnecessary buffers can also contribute to area recovery.

11. How can IR drop be managed by adjusting the number of power straps? While increasing the number of power straps reduces IR drop, what is the optimal number of straps to implement? How is the required number of straps calculated? What potential issues may arise from an excessive number of straps?

A. Tools such as Voltagestrom and Redhawk can be utilized to calculate IR drop if it is excessive. Based on the results, additional straps can be added. Through repeated project experience, the appropriate number of straps can be determined without the need for these tools. While calculations exist, they are approximate. An excessive number of straps can lead to routing congestion and impact the area. For further details on determining the number of power straps required for a design, please refer to the provided link.

12. aprPGConnect is used for the logical connection of all VDD and VSS nets of all modules. How are all VDD and VSS nets connected to the global VDD/VSS nets before placement?

A.

The aprPGConnect facilitates the logical connection of all VDD and VSS nets across all modules. This is for physical connection.

CCS vs. NLDM: A Comparison of Delay Models

Introduction to Delay Models

• CCS stands for Composit Current Sourse Model, and NLDM stands for Non-Linear Delay Model.

• Both CCS & NLDM are delay models used in timing analyze.

Key Differences in Driver Modeling

• NLDM uses a voltage source for driver modeling

• CCS uses a current source for driver modeling

Advantages of CCS over NLDM

• The issues with NLDM modeling is that, when the drive resistance RD becomes much less than Znet(network load impedance), then ideal condition arises i.e Vout=Vin.

• Which is impossible in practical conditions.

• So with NLDM modeling parameters like the cell delay calculation, skew calculation will be inaccurate.

• That is the reason why we prefer CCS to NLDM

Physical Cells :TAP CELLS, TIE CELLS, ENDCAP CELLS, DECAP CELLS

Tap Cells (Well Taps) : These library cells connect the power and ground connections to the substrate and n­wells, respectively. 

By placing well taps at regular intervals throughout the design, the n­well potential is held constant for proper electrical functioning. The placer places the cells in accordance with the specified distances and automatically snaps them to legal positions (which are the core sites).

All the cells discussed in these post are called Physical only cells, as these cells are not important with respect to Funtional Design. These were invented to Complete the Design properly. These cells does not have any timing constains. There are different types of physical cells. Let us see the usage of different cells

TIE CELLS: Tie High and Tie Low cells are used to connect the gate of the transistor to either power or ground. In Lower technology nodes, if the gate is connected to  power/ground the transistor might be turned on/off dure to power or ground bounce. These cells are part of standard cell library. The cells which required Vdd connected to Tie high cells. The cells which require Vss/Gnd connected to Tie low cells. These cells are basically present in the ".lib"

• Floating nets or unused nets need to be tied with some constant value (0 or 1), can be achieved using Tie cells
• Using connect_tie_cells command, we can inser a tie cell in the design during the PNR

TIE HIGH CELLS:

Using these cells we directly connect the VDD to the gate transistor, now we connect the O/P of these cells to the transistor gate if any fluctuations in VDD due to ESD then PMOS circuit pull it back to stable state. PMOS should be ON always, the I/P of the PMOS transistor is coming from the O/P of NMOS transistor and For NOMS gate and drain are shorted and NMOS will be in saturation mode which act as a pull down circuit and always gives a low voltage at the gate of PMOS. Now PMOS will on and gives stable high output and this output is connected to the gate of transistor

ENDCAP CELL: These Library cells do not have signal connectivity. They connect only to power and ground rails once power rails created in design. They also ensure that gaps do not occur between the well and implant layers. This prevents DRC violations by satisfying well tie off requirements for the core rows. Each end of the core row, left and right can have only one ENDCAP cell

Hower you can specify a list of different END CAPS for inserting horizontal ENDACP lines, which terminate the top and bottom boundaries of object such as macros. A core row can be fragmented (contains gaps), since row donot intersect objects such as power domains. For this, the tool places ENDCAP cells on both ends of the unfragmented segment.

    

• To Protect the gate of a standard cell placed near the boundary from damage during manufacturing
• To Avoid the base layer DRC(Nwell and Implant Layer) at the boundary
• To make the proper alignment with other block
• Some standard cell library has END CAP cell which serve as Decap cell as well

DeCAP CELLS: These are temporary capacitors added in the design between power and ground rails to counter functional failures due to dynamic IR Drop. Dynamic IR Drop happens at the active edge of the clock at which a high % of sequential and Digital elements switch . Due to this simultaneous switching a high current is drawn from the power grid for a small duration. if the power source is far away from a flop, then there are high chances of this flop to move into metastable state due to IR Drop. To overcome this DECAPS are added. At the active edge of clock when the current requirement is high, these DECAPS discharges and provide boost to the power grid. One major disadvantage in usage of DECAPS is that these add leakage current in the circuit. DECAPS are placed as fillers. The closer they are to the flops, the better it is.

DeCAP Cells are typically poly gate transistors where source and drain are connected to the ground rail, and gate is connected to the power rail

When there is an instantaneous switching activity the charge required moves from intrinsic and extrinsic local charge reservoirs as oppose to voltage sources. Extrinsic capacitances are DECAP cells placed in the Design. Intrinsic capacitances are those present naturally in the circuit, such as the grid capacitance, the variable capacitance inside nearby logic, and the neighborhood loading capacitance exposed when the P or N channel are open

One drawback of DECAP cells is that they are very leaky, so the more decap cells the more leakage. Another drawback, which many designers ignore , is the interaction of the decap cells with the package RLC network. Since the die is essentially a capacitor with very small R & L, the package is a hug RL network, the more decap cells placed the more chance of tuning the circuit into its resonance frequency. That would cause a trouble, since both the VDD and GND will be oscillating. Few Design were failed because the DECAP cells placed near high activity clock buffers. Most recommended option is a decap optimazation flow where the tool will study charge requirements at every moment in time and figure out how much decap to place at any node. This should be done while taking package models into a account to ensure resonance frequency is not hit

 

   

What is Verilog

 What is Verilog?

Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. 

A brief history 

Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway  Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu  Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil   Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally  acquired by Cadence Design Systems, San Jose, CA in 1989. 

Verilog was invented as simulation language. Use of Verilog for synthesis was a complete  afterthought 

Cadence Design Systems decided to open the language to the public in 1990, and thus OVI  (Open Verilog International) was born. Till that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog  simulators. The first of these came to market in 1992, and now there are mature Verilog  simulators available from several sources. 

As a result, the Verilog market has grown substantially. The market for Verilog related tools in  1994 was well over $75m, making it the most commercially significant hardware description language on the market. 

An IEEE working group was established in 1993 under the Design Automation Sub-Committee  to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.

The Verilog Standard was revised in 2001 and it became IEEE Standard 1364-2001

WHAT IS SYNTHESIS IN DIGITAL DESIGN

 Synthesis

Synthesis: It is a process to map and optimizing higher level HDL description to technology cells (gates, flip flops etc.)

Synthesis Flow Diagram:

HDL Description: This is description of design in Verilog. One has to use subset of constructs as synthesis tools does not support all of them.

Technology Library: This file contains functional description and other information related to area and speed for all the cells of particular technology.

Here "technology" means information about particular process for particular vendor. For example Company X, Standard Cell, 0.18 micron, Y Process, Z Type.

Constraints: This optional file contains information about physical expectations from design. For example speed and area.

Netlist: A netlist is a text file description of a physical connection of components.

Reports: This optional output file contains physical performance of design in terms of speed and area.

Schematic: Some tools provide the facility to view netlist in terms of schematics for better understanding of design and to match the results with the expectations.

Simple example:
Following trivial example explains the Synthesis process. In this example only always procedural statement is used.

module test (out, in1, in2); // behavioral description
  input in1, in2;
  output out;
  reg out;
  reg temp;                 // temporary register

  always@(in1 or in2) begin
    temp = ~in2;
    out = ~in1 ^ temp;  // I am trying to have exor with inverted 
  end                   // inputs
endmodule

after synthesis one gets following "netlist" in verilog. Note that XOR2 is module picked up from technology library. It will be different for different libraries.

module add ( out , in1 , in2 );  // netlist

    output out ;
    input in1 ;
    input in2 ;

    XOR2   instance_name (.Y (out ),.A (in1 ),.B (in2 ) );

endmodule

VERILOG CODE FOR D FLIP FLOP

The Verilog beginners need examples of simple building blocks to learn coding techniques. Now  we will go through different implementation of D FLIP FLOP

=========================================================================

1.Simple D FLIP FLOP 

module dff (data, clock, q);
    // port list
    input   data, clock;
    output  q;

    // reg / wire declaration for outputs / inouts     
    reg     q;

    // logic begins here
    always @(posedge clock) 
        q <= data;
endmodule

========================================================================

2. D Type Flip-flop with asynchronous reset

module dff_async (data, clock, reset, q);

    // port list
    input   data, clock, reset;
    output  q;

    // reg / wire declaration for outputs / inouts
    reg     q;

    // reg / wire declaration for internal signals

    // logic begins here
    always @(posedge clock or negedge reset)
        if(reset == 1'b0)
            q <= 1'b0;
        else 
            q <= data;
endmodule

=======================================================================

3. D Type Flip-flop with Synchronous reset

module dff_sync (data, clock, reset, q);
    // port list
    input   data, clock, reset;
    output  q;

    // reg / wire declaration for outputs / inouts
    reg     q;

    // reg / wire declaration for internal signals

    // logic begins here
    always @(posedge clock) 
        if(reset == 1'b0)
            q <= 1'b0;
        else 
            q <= data;
endmodule

================================================================================

4.D Type Flip-flop with asynchronous reset and clock enable

module dff_cke (data, clock, reset, cke, q);
    // port list
    input   data, clock, reset, cke;
    output  q;

    // reg / wire declaration for outputs / inouts
    reg     q;

    // logic begins here
    always @(posedge clock or negedge reset) 
        if (reset == 0)
            q <= 1'b0;
        else if (cke == 1'b1)
            q <= data;
endmodule

Vlsi Design Styles in Digital Design

Digital Design can be implemented by various design styles. And depending on the market requirement different design styles are used.

• Programmable Logic Design
  • Field Programmable Gate Array (FPGA)
  • Gate Array
• Standard Cell (semi custom design)
• Full Custom Design

• Field Programmable Gate Array (FPGA):
  • Using VHDL or verilog
  • Implementation
    • Placement and Routing
    • BitStream Generation
    • Analyse timing, view layout, simulations etc
• Gate Array: Gate Array design implementation is done with metal design and processing. The implementation requires two-step manufacturing process
  • First phase, which is based on standard masks, results in an array of uncommitted transistors on each GA chips
  • These uncommitted chips can be customized later, which is completed by defining the metal interconnects between the transistor of the array
  • In this chip utilization factor is higher than that of FPGA
  • Chip speed is higher
• Standard Cell or Semi Custom Design:
  • The standard-cells based design is often called semi custom design.
  • The cells are pre-designed for general use and the same cells are utilized in many different chip designs. 
• Full Custom Design
• Full custom design involves creating IC where each individual transistors architecture and interconnections are specified. Designers manually place transistors, resistors,capacitors and other components at the transistor level

STANDARD CELLS IN DIGITAL DESIGN/VLSI

Standard cell are well defined cells which are used in Digital Design more frequently. To name few AND, NOR, NAND, XOR ,etc belongs to standard cell family. All the standard cells from one library will have equal drive strength  and  equal height. Standard cell Architecture is defined based on  cell height which is determined on the basis of the number of trackes , beta ratio, pitch and transistor widths. To attain the similarity amoung the cells and aboid the alignment issues ,standard cells are designed with fixed height

The height of a standard cell can be calculated by considering number of tracks required for power rail, ground rail, I/O pins and routing. Often the standard cells are available in single height and double height. The Double height cells are the high density cells and are used for ultra high speed operations 

STANDARD CELL DESIGN METHODOLOGY

• VDD and GND should be of same height and parallel. Both the power rails used metal M1
• make sure within the cell all the PMOS should occupy top and all NMOS should occupy bottom of the Layout
• Preferred Practice:  Diffusion layer for all the transistor in a row
• All the gates include the gate and substrate

 Layout for any schematic can be drawn in many ways. Layout of INVERTER can be drawn in two different ways.

In the Fig 2 was preferred layout as all the PMOS will be in one level and all the NOMS will be at one level, and also the poly gates are drawn vertical and these are common to nmos and pmos transistors. 

One more layout example with NAND GATE

There are many reasons for choosing the FIG 2 and FIG 3 as most preferred Layout

• Save the Design Area: Both the nwell and pwell are in the same level for all the standard cell, so make a common well which saves lots of areas 
• Easy Placement for APR tool: All the standard cells have the same height and easily can be fit into the standard cell row so make it easy for APR (Automatic Place and Route) to place them. They also have power rails in the same location for all the standard cells, so power rails can also be abutted easily 
• Easy to Route: All the pins of standard cells are in the intersection of horizontal and vertical tracks, So it becomes easy to route them by the APR tool . 

Different Cells in Digital Design

 In any digital design apart from the standard cell , we need to different Physical Cell to minimize the issues in the design. 

• Standard Cells
• Tap Cells
• End cap Cells
• ICG Cells
• DECAP Cells
• Filler Cells
• ESD Clamps
• Tie Cells
• Spare Cells
• Delay Cells
• Metrology Cells

CROSS TALK

Crosstalk noise: noise refers to undesired or unintentional effect between two or more signals that are going to affect the proper functionality of the chip. It is caused by capacitive coupling between neighboring signals on the die. In deep submicron technologies, noise plays an important role in terms of functionality or timing of device due to several reasons.

• Increasing the number of metal layers. For example, 28nm has 7 or 8 metal layers and in 7nm it’s around 15 metal layers.
• Vertically dominant metal aspect ratio it means that in lower technology wire are thin and tall but in higher technology the wire is wide and thin, thus a greater the proportion of the sidewall capacitance which maps into wire to wire capacitance between neighboring wires.
• Higher routing density due to finer geometry means more metal layers are packed in close physical proximity.
• A large number of interacting devices and interconnect.
• Faster waveforms due to higher frequencies. Fast edge rates cause more current spikes as well as greater coupling impact on the neighboring cells.
• Lower supply voltage, because the supply voltage is reduced it leaves a small margin for noise.
• The switching activity on one net can affect on the coupled signal. The effected signal is called the victim and affecting signals termed as aggressors.

There are two types of noise effect caused by crosstalk

• Glitch: when one net is switching and another net is constant then switching signal may cause spikes on the other net because of coupling capacitance (Cc) occur between two nets this is called crosstalk noise.

In fig the positive glitch is induced by crosstalk from rising edge waveform at the aggressor net. The magnitude of glitch depends on various factors.

• Coupling capacitance between aggressor and victim net: greater the coupling capacitance, larger the magnitude of glitch.
• Slew (transition) of the aggressor net: if the transition is more so magnitude of glitch also more. And we know the transition is more because of high output drive strength.
• If Victim net grounded capacitance is small then the magnitude of glitch will be large.
• If Victim net drive strength is small then the magnitude of glitch will be large.

Types of glitches:

• Rise: when a victim net is low (constant 0) and the aggressor net is at a rising edge.

• Fall: when a victim net is high (constant 1) and the aggressor net is at the falling edge.

• Overshoot: when a victim net is high (constant 1)) and the aggressor net is at a rising edge.

• Undershoot: when a victim net is low (constant 0) and the aggressor net is at the falling edge.

Crosstalk delay: 

when both nets are switching or in transition state then switching signal at the victim signal may have some delay or advancement in the transition due to coupling capacitance (Cc) occur between two nets this is called crosstalk delay.
Crosstalk delay depends on the switching direction of aggressor and victim net because of this either transition is slower or faster of the victim net.


Types of crosstalk:
Positive crosstalk: the aggressor net has a rising transition at the same time when the victim net has a falling transition. The aggressor net switching in the opposite direction increases the delay for the victim. The positive crosstalk impacts the driving cell, as well as the net, interconnect - the delay for both gets increased because the charge required for the coupling capacitance Cc is more.

Negative crosstalk: the aggressor net is a rising transition at the same time as the victim net. The aggressor's net switching in the same direction decrease delay of the victim. The positive crosstalk impacts the driving cell, as well as the net, interconnect - the delay for both gets decreased because the charge required for the coupling capacitance Cc is less.

Crosstalk effect on timing analysis:

Consider crosstalk in data path:
If the aggressor transition in the same direction as the victim then victim transition becomes fast because of this data will be arrive early means arrival time will be less.
Setup = RT – AT(dec) this is good for setup #dec- decrease
Hold = AT(dec) – RT this is bad for hold

If the aggressor transition in a different direction as a victim then victim transition becomes slow because of this data will be arrive late means arrival time will be more.


Setup = RT – AT(inc) this is not good for setup
Hold = AT(inc) – RT this is good for hold #inc- increase

Consider crosstalk in the clock path:
If the aggressor transition in the same direction as the victim then victim transition becomes fast because of this clock will be arrive early means Required time will be less.

Setup = RT(dec) – AT this is not good for setup

Hold = AT – RT(dec) this is good for hold

If the aggressor transition in a different direction as a victim then victim transition becomes slow because of this clock will be arrive late means the Required time will be more.

Setup = RT(inc) – AT this is good for setup

Hold = AT – RT(inc) this is not good for hold

How to reduce the crosstalk:

• Wire spacing (NDR rules) by doing this we can reduce the coupling capacitance between two nets.
• Increased the drive strength of victim net and decrease the drive strength of aggressor net
• Jumping to higher layers (because higher layers have width is more)
• Insert buffer to split long nets
• Use multiple vias means less resistance then less RC delay
• Shielding: high-frequency noise is coupled to VSS or VDD since shielded layers are connects to either VDD or VSS. The coupling capacitance remains constant with VDD or VSS.

Clock Uncertainty

Clock Uncertainty : The Time difference between the arrival of the clock signal at the register in one clock domain or between any two clock domains


Uncertainty is caused by following factors:

• clock skew
• clock jitter
• cross talk

Clock Skew

• Skew is the difference in clock arrival time across the chip.
• Clock Skew is the temporal difference between the arrival of the same edge of a clock signal at the Clock pin of the capture and launch flops.
• Signal takes time to move from one location to another. Clock latency is the time taken by a clock signal to move from the clock source to the clock pin of a particular flip-flop. Clock skew can alternatively be defined as the difference between capture and launch flop delay.

For example, The capture clock delay is 2.5ns while the launch clock latency is 0ns. The difference between them is 2.5ns-0ns = 2.5ns, which is the clock skew value

The clock should ideally reach the clock pin of all the flip-flops in a design at the same time, resulting in a zero skew. However, this is not attainable owing to varying wire-interconnect lengths and temperature changes.

What is the reason for skew in a design?

A skew in a design occurs when a flip-flop is put near the clock source and another flip-flop is placed at the far end of the core region. In practice, the skew cannot be zero due to the disparity in connecting lengths. To address this, a user-specified number is provided to obtain correct pre-CTS timing data. After the clock tree is constructed, the real skew values are accessible, and the uncertainty is limited to the Jitter value alone.

The time difference/delta between the launch flip flop and capture flip flop or
it refers to the absolute time diff between the clock signal arrival between the two points in the clock network

Tskew =Tlaunch_clk - Tcapture_clk

skew can be classified into different skews:

•  +ve skew: Positive clock skew, In this case, the capture clock delay is greater than the launch clock latency. Positive skew is advantageous for setup timing. Due to the inclusion of skew, the capture clock is delayed by a few ns. Therefore the timing path requires one clock period and Skew margin to match the setup requirement.
• -ve skew: Negative Skew is beneficial for hold time since it delays the fresh launch. Because of the delay in launching the new data, the prior data will be effectively recorded and will not be overwritten. However, negative skew is detrimental to setup timing.
• Local skew: The disparity in latency between two related flops in a design is referred to as local skew.
• Global skew: is the difference in clock delay between two unrelated flops or the difference between the longest and shortest clock paths in the design.
• Usefull Skew :Useful skew is the skew that is purposefully introduced into the design to satisfy timing. It is particularly introduced in clock pathways where timing is failing, so that timing is passed in that path. However, useful skew cannot be applied arbitrarily. This must be done with caution, ensuring that the margin is accessible in both the preceding and subsequent time paths. The uncontrolled insertion of skew might result in further timing violations rather than resolving them. It may be used to correct both setups and hold errors 

Cock Jitter

It can be defined as “deviation of a clock edge from its ideal location.” Clock jitter is typically caused by clock generator circuitry, noise, power supply variations, interference from nearby circuitry etc. Jitter is a contributing factor to the design margin specified for timing closure.
Based on how it is measured in a system, jitter is of following types:
Period jitter
Period jitter is the deviation in cycle time of a clock signal with respect to the ideal period over a number of randomly selected cycles(say 10K cycles). It can be specified an average value of of clock period deviation over the selected cycles(RMS value) or can be the difference between maximum deviation & minimum deviation within the selected group(peak-to-peak period jitter).

Cycle to cycle jitter : 

C2C is the deviation in cycle of of two adjacent clock cycles over a random number of clock cycles. (say 10K). This is typically reported as a peak value within the random group.This is used to determine the high frequency jitter.
 

Phase jitter:

In frequency domain, the effect being measured is phase noise. It is the frequency domain representation of rapid, short-term, random fluctuations in the phase of a waveform. This can be translated to jitter values for use in digital design.

Please note all the above jitters are effectively the same phenomenon, but different way of measuring and representing the effect for use in design flow. The jitter number thus obtained is used to specify the design margin using the command “set_clock_uncertainty”.

Effects
Since the jitter affects the clock delay of the circuit and the time the clock is available at sync points, setup and hold of the path elements are affected by it. Depending on whether the jitter causes the clock to be slower or faster, there can be setup hold or setup violations in an otherwise timing clean system. This will in turn lead to performance or functional issues for the chip. So it is necessary that the designer knows the jitter values of the clock signal and need to be considered while analyzing timing.

Cross Talk

Swtiching of the signal in one net will effect the signal in neighboring net due to cross coupling capacitance, know as Cross Talk. This noise will affect the functionality of chip 

PD MCQ 2

PD MCQ

Behavioral Modeling I

Behavioral modeling is the highest level of abstraction in the Verilog HDL. The other modeling techniques are relatively detailed. They require some knowledge of how hardware, or hardware signals work. The abstraction in this modeling is as simple as writing the logic in C language. This is a very powerful abstraction technique. All that designer needs is the algorithm of the design, which is the basic information for any design.

Most of the behavioral modeling is done using two important constructs: initial and always. All the other behavioral statements appear only inside these two structured procedure constructs.

The initial Construct

The statements which come under the initial construct constitute the initial block. The initial block is executed only once in the simulation, at time 0. If there is more than one initial block. Then all the initial blocks are executed concurrently. The initial construct is used as follows:

initial
begin
reset = 1'b0;
clk = 1'b1;
end

or

initial
clk = 1'b1;

In the first initial block there are more than one statements hence they are written between begin and end. If there is only one statement then there is no need to put begin and end.

The Always Construct

The statements which come under the always construct constitute the always block. The always block starts at time 0, and keeps on executing all the simulation time. It works like a infinite loop. It is generally used to model a functionality that is continuously repeated.

always
#5 clk = ~clk;

initial
clk = 1'b0;

The above code generates a clock signal clk, with a time period of 10 units. The initial blocks initiates the clk value to 0 at time 0. Then after every 5 units of time it toggled, hence we get a time period of 10 units. This is the way in general used to generate a clock signal for use in test benches.

always @(posedge clk, negedge reset)
begin
a = b + c;
    d = 1'b1;
end

In the above example, the always block will be executed whenever there is a positive edge in the clk signal, or there is negative edge in the reset signal. This type of always is generally used in implement a FSM, which has a reset signal.

always @(b,c,d)
begin
    a = ( b + c )*d;
    e = b | c;
end

In the above example, whenever there is a change in b, c, or d the always block will be executed. Here the list b, c, and d is called the sensitivity list.

In the Verilog 2000, we can replace always @(b,c,d) with always @(*), it is equivalent to include all input signals, used in the always block. This is very useful when always blocks is used for implementing the combination logic