Double Patterning

Double patterning is a lithographic technique employed in advanced integrated circuit manufacturing processes. It allows for the creation of sub-nanometer features on chips using existing optical lithography systems.

The implementation of double patterning presents certain challenges, including elevated mask and lithography expenses, and constraints on circuit layout, which can affect design complexity, device performance, variability, and density.

Double patterning mitigates diffraction effects in optical lithography, which arise because the minimum dimensions of advanced process nodes are significantly smaller than the 193nm wavelength of the light source. These diffraction effects compromise the accuracy of deep sub-micron patterns, causing blurring and potentially preventing the replication of small features from the mask onto the wafer.

To mitigate diffraction effects, such as shorts and opens, the original mask is partitioned into two distinct masks, designated as Mask A and Mask B. This approach, however, escalates mask costs (lithography expenses) due to the implementation of double patterning and introduces additional Design Rule Checking (DRC) constraints.

To address the increasingly significant diffraction challenges associated with each new process node, several reticle enhancement techniques have been developed.

Phase-shift masks, introduced at the 180nm process node, modify the phase of light passing through specific mask regions. This alteration influences diffraction patterns, thereby mitigating the defocusing effects associated with mask dimensions smaller than the illumination wavelength. A drawback of phase-shift techniques is the increased complexity and cost of mask fabrication.

Optical Proximity Correction (OPC) techniques involve pattern distortion on the mask to counteract diffraction effects. This is achieved, for example, by adding small "ears" to the corners of a square feature on the mask, ensuring sharp definition on the wafer. While effective, this technique introduces layout restrictions, computational overhead in design, and increases the time and cost associated with mask production..

TIE CELLS

To prevent direct gate connections to the power or ground network, tie-high and tie-low cells are employed. Within this design, certain cell inputs may necessitate a logic 0 or logic 1 value. Unused cell inputs are also connected to ground or power nets, as leaving them unconnected is not permissible. Rather than directly connecting these inputs to the VDD/VSS rails/rings, they are connected to specialized cells within the library, known as TIE cells

The tie-high, tie-low circuit, featuring tie-high and tie-low outputs, incorporates a regenerative device designed for connection to both outputs, along with at least one PMOS device and one NMOS device, intended for connection to a high voltage and a low voltage, respectively.

In integrated circuit (IC) applications, it is not always necessary to utilize all inputs. Unused inputs should be consistently maintained in a stable logic state, rather than left floating, as unpredictable or intermediate logic states can lead to unpredictable and inconsistent logical outcomes. This is a critical concern that IC designers actively address.

To ensure stability, small circuits are incorporated into ICs. These circuits typically provide at least two outputs: one consistently high and another consistently low. These outputs are then used to connect IC inputs to either a high or low state, thereby locking unused inputs into a stable logic state.

However, conventional circuit designs present several challenges. Many designs utilize at least four transistors, which consume valuable chip area and may necessitate additional, costly manufacturing steps. Furthermore, some designs, while using only three transistors, often exhibit limited tolerance to electrostatic discharge (ESD).

Consequently, there is a need in the field of integrated circuit design for improved, smaller circuits with enhanced ESD tolerance, capable of effectively tying unused IC inputs to either a high or low state.

Regarding the rationale for employing such circuits, gate oxide is inherently thin and sensitive to voltage surges. Certain manufacturing processes may restrict the direct connection of gates to power rails due to the potential for gate oxide damage from voltage surges, such as ESD events. Therefore, tie cells, which utilize diode-connected n-type or p-type devices, are often employed. This approach prevents direct gate connections to either power or ground.

This is the foundry's rationale for ESD protection against surges. Examining the schematic of the tie cells in a standard cell library may reveal an inverter configuration with its input connected to either VDD (for tie-low) or VSS (for tie-high). While this configuration still connects the tie cell's gate to the power rails, it offers benefits such as reduced leakage current. Additionally, it simplifies the process of rewiring during Engineering Change Orders (ECOs), particularly when swapping a 1'b1 for a 1'b0.

Skin Effect Impact on Semiconductor Wires

Currently, our analysis has assumed a linear and constant resistance for a semiconductor wire, which is generally accurate for most semiconductor circuits. However, at elevated frequencies, the skin effect introduces a frequency-dependent resistance.

High-frequency currents exhibit a tendency to concentrate on the conductor's surface, with current density decreasing exponentially with depth. The skin depth, denoted as d, is defined as the depth at which the current diminishes to e⁻¹ of its nominal value, and is expressed as:

Given the signal frequency (f) and the permeability of the surrounding dielectric (U), which typically approximates the permeability of free space (m = 4p ´ 10-7 H/m), the skin depth for Aluminum at 1 GHz is calculated to be 2.6 mm.

The impact of the skin effect can be approximated by assuming a uniform current distribution within an outer shell of the conductor, with a thickness denoted as d, as illustrated in the provided figure for a rectangular wire. Consequently, the effective cross-sectional area of the wire is approximated to 

we obtain the following expression for the resistance (per unit length) at high frequencies (f > fs):

The increased resistance at higher frequencies may cause an extra attenuation and hence distortion of the signal being transmitted over the wire. To determine the on-set of the skin-effect, we can find the frequency fs where the skin depth is equal to half the largest dimension (W or H) of the conductor. Below fs the whole wire is conducting current, and the resistance is equal to (constant) low-frequency resistance of the wire. From Eq. (4.6), we find the value of fs:

Physical design QNA

1. What is floorplanning?

    A. Floorplanning is the process of strategically positioning blocks and macros within the chip or core area, thereby defining routing regions. This process determines the die size and establishes wire tracks for standard cell placement. It also generates power straps and specifies Power Ground (PG) connections, as well as I/O pin/pad placement information. In essence, floorplanning involves determining macro placement, power grid generation, and I/O placement.

2. What constitutes a well-executed floorplan?

    A. A robust floorplan should adhere to the following constraints:

    * Minimize the overall chip area.

    * Facilitate the routing phase (ensuring routability).

    * Enhance performance by reducing signal delays.

3. What inputs are required for floorplanning?

    A. The following inputs are essential for floorplanning:

    * Synthesized Netlist (.v, .vhdl)

    * Design Constraints (SDC – Synopsys Design Constraints)

    * Physical Partitioning Information of the design

    * IO Placement file (optional)

    * Macro Placement File (optional)

    * Floorplanning Control parameters

4. What are the outputs of the floorplanning process?

    A. The floorplanning process yields the following outputs:

    * Die/Block Area

    * I/Os Placement

    * Macros Placement

    * Power Grid Design

    * Power Pre-routing

    * Standard cell placement areas

5. Given a netlist comprising 500k gates, how can the die area and floorplanning be estimated?

    A. There are two primary methods for estimating die area:

    Method 1:

    Each cell possesses an area value specific to the chosen library. By examining each cell and multiplying its count by its corresponding area from the vendor's library, a density factor can be applied. Typically, a standard design achieves approximately 80% density after placement. This data allows for an estimation of the required die area.

    Method 2:

    Alternatively, the design can be loaded into an implementation tool. By adjusting the floorplan (x and y coordinates), the initial utilization can be set to approximately 50% to 60%.

The approach is contingent upon the quality and completion status of the netlist, specifically the degree of completion, such as 75%, 80%, or 90%.

6. What is the methodology for floor planning in multi-Vdd designs?

A. The initial step involves defining the power domains, followed by the implementation of power rings for each domain and the addition of power stripes to supply power to standard cells.

7. What is the definition of core utilization percentage?

A. The core utilization percentage represents the proportion of the core area utilized for cell placement. This is calculated as the ratio of the total cell area (including hard macros, standard cells, and soft macro cells) to the core area. For instance, a core utilization of 0.8 indicates that 80% of the core area is used for cell placement, with 20% available for routing.

8. Does an increase in core utilization to 90% potentially lead to macros being placed outside the core area, and does this imply a reduction in width and height?

A. Operating at 90% utilization may introduce congestion and routing challenges, potentially hindering routing within the designated area. While it may be feasible to accommodate this utilization level initially, subsequent timing optimizations, such as upsizing and buffer insertion, can increase the size requirements. In such cases, adjustments to the floorplan may be necessary. Therefore, a safer approach is to maintain a utilization range of 70% to 80%.

9. Why is it necessary to remove all placed standard cells and then write out the floorplan in DEF format? What is the purpose of the DEF file?

A. The DEF file primarily focuses on the floorplan size. This method is employed to obtain an abstract representation of the floorplan. By saving and loading this file, the abstract can be restored, eliminating the need to redo the floorplan.

10. Can area recovery be achieved by downsizing cells along paths with positive slack?

A. Yes, area recovery can be accomplished by downsizing cells on paths exhibiting positive slack. Additionally, the removal of unnecessary buffers can also contribute to area recovery.

11. How can IR drop be managed by adjusting the number of power straps? While increasing the number of power straps reduces IR drop, what is the optimal number of straps to implement? How is the required number of straps calculated? What potential issues may arise from an excessive number of straps?

A. Tools such as Voltagestrom and Redhawk can be utilized to calculate IR drop if it is excessive. Based on the results, additional straps can be added. Through repeated project experience, the appropriate number of straps can be determined without the need for these tools. While calculations exist, they are approximate. An excessive number of straps can lead to routing congestion and impact the area. For further details on determining the number of power straps required for a design, please refer to the provided link.

12. aprPGConnect is used for the logical connection of all VDD and VSS nets of all modules. How are all VDD and VSS nets connected to the global VDD/VSS nets before placement?

A.

The aprPGConnect facilitates the logical connection of all VDD and VSS nets across all modules. This is for physical connection.

CCS vs. NLDM: A Comparison of Delay Models

Introduction to Delay Models

• CCS stands for Composit Current Sourse Model, and NLDM stands for Non-Linear Delay Model.

• Both CCS & NLDM are delay models used in timing analyze.

Key Differences in Driver Modeling

• NLDM uses a voltage source for driver modeling

• CCS uses a current source for driver modeling

Advantages of CCS over NLDM

• The issues with NLDM modeling is that, when the drive resistance RD becomes much less than Znet(network load impedance), then ideal condition arises i.e Vout=Vin.

• Which is impossible in practical conditions.

• So with NLDM modeling parameters like the cell delay calculation, skew calculation will be inaccurate.

• That is the reason why we prefer CCS to NLDM

Physical Cells :TAP CELLS, TIE CELLS, ENDCAP CELLS, DECAP CELLS

Tap Cells (Well Taps) : These library cells connect the power and ground connections to the substrate and n­wells, respectively. 

By placing well taps at regular intervals throughout the design, the n­well potential is held constant for proper electrical functioning. The placer places the cells in accordance with the specified distances and automatically snaps them to legal positions (which are the core sites).

All the cells discussed in these post are called Physical only cells, as these cells are not important with respect to Funtional Design. These were invented to Complete the Design properly. These cells does not have any timing constains. There are different types of physical cells. Let us see the usage of different cells

TIE CELLS: Tie High and Tie Low cells are used to connect the gate of the transistor to either power or ground. In Lower technology nodes, if the gate is connected to  power/ground the transistor might be turned on/off dure to power or ground bounce. These cells are part of standard cell library. The cells which required Vdd connected to Tie high cells. The cells which require Vss/Gnd connected to Tie low cells. These cells are basically present in the ".lib"

• Floating nets or unused nets need to be tied with some constant value (0 or 1), can be achieved using Tie cells
• Using connect_tie_cells command, we can inser a tie cell in the design during the PNR

TIE HIGH CELLS:

Using these cells we directly connect the VDD to the gate transistor, now we connect the O/P of these cells to the transistor gate if any fluctuations in VDD due to ESD then PMOS circuit pull it back to stable state. PMOS should be ON always, the I/P of the PMOS transistor is coming from the O/P of NMOS transistor and For NOMS gate and drain are shorted and NMOS will be in saturation mode which act as a pull down circuit and always gives a low voltage at the gate of PMOS. Now PMOS will on and gives stable high output and this output is connected to the gate of transistor

ENDCAP CELL: These Library cells do not have signal connectivity. They connect only to power and ground rails once power rails created in design. They also ensure that gaps do not occur between the well and implant layers. This prevents DRC violations by satisfying well tie off requirements for the core rows. Each end of the core row, left and right can have only one ENDCAP cell

Hower you can specify a list of different END CAPS for inserting horizontal ENDACP lines, which terminate the top and bottom boundaries of object such as macros. A core row can be fragmented (contains gaps), since row donot intersect objects such as power domains. For this, the tool places ENDCAP cells on both ends of the unfragmented segment.

    

• To Protect the gate of a standard cell placed near the boundary from damage during manufacturing
• To Avoid the base layer DRC(Nwell and Implant Layer) at the boundary
• To make the proper alignment with other block
• Some standard cell library has END CAP cell which serve as Decap cell as well

DeCAP CELLS: These are temporary capacitors added in the design between power and ground rails to counter functional failures due to dynamic IR Drop. Dynamic IR Drop happens at the active edge of the clock at which a high % of sequential and Digital elements switch . Due to this simultaneous switching a high current is drawn from the power grid for a small duration. if the power source is far away from a flop, then there are high chances of this flop to move into metastable state due to IR Drop. To overcome this DECAPS are added. At the active edge of clock when the current requirement is high, these DECAPS discharges and provide boost to the power grid. One major disadvantage in usage of DECAPS is that these add leakage current in the circuit. DECAPS are placed as fillers. The closer they are to the flops, the better it is.

DeCAP Cells are typically poly gate transistors where source and drain are connected to the ground rail, and gate is connected to the power rail

When there is an instantaneous switching activity the charge required moves from intrinsic and extrinsic local charge reservoirs as oppose to voltage sources. Extrinsic capacitances are DECAP cells placed in the Design. Intrinsic capacitances are those present naturally in the circuit, such as the grid capacitance, the variable capacitance inside nearby logic, and the neighborhood loading capacitance exposed when the P or N channel are open

One drawback of DECAP cells is that they are very leaky, so the more decap cells the more leakage. Another drawback, which many designers ignore , is the interaction of the decap cells with the package RLC network. Since the die is essentially a capacitor with very small R & L, the package is a hug RL network, the more decap cells placed the more chance of tuning the circuit into its resonance frequency. That would cause a trouble, since both the VDD and GND will be oscillating. Few Design were failed because the DECAP cells placed near high activity clock buffers. Most recommended option is a decap optimazation flow where the tool will study charge requirements at every moment in time and figure out how much decap to place at any node. This should be done while taking package models into a account to ensure resonance frequency is not hit

 

   

What is Verilog

 What is Verilog?

Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. 

A brief history 

Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway  Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu  Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil   Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally  acquired by Cadence Design Systems, San Jose, CA in 1989. 

Verilog was invented as simulation language. Use of Verilog for synthesis was a complete  afterthought 

Cadence Design Systems decided to open the language to the public in 1990, and thus OVI  (Open Verilog International) was born. Till that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog  simulators. The first of these came to market in 1992, and now there are mature Verilog  simulators available from several sources. 

As a result, the Verilog market has grown substantially. The market for Verilog related tools in  1994 was well over $75m, making it the most commercially significant hardware description language on the market. 

An IEEE working group was established in 1993 under the Design Automation Sub-Committee  to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.

The Verilog Standard was revised in 2001 and it became IEEE Standard 1364-2001